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1 for more information www.linear.com/LTC3626 typical a pplica t ion fea t ures descrip t ion 20v , 2.5a synchronous monolithic step-down regulator with current and temperature monitoring the lt c ? 3626 is a high efficiency, monolithic synchronous buck regulator using a phase-lockable controlled on-time, current mode architecture capable of supplying up to 2.5a of output current . the operating supply voltage range is 3.6v to 20v, making it suitable for a wide range of power supply applications. the operating frequency is programmable from 500khz to 3mhz with an external resistor allowing the use of small surface mount inductors . for applications sensitive to switching noise , the LTC3626 can be externally synchro - nized over the same frequency range. an internal phase- locked loop aligns the on-time of the top power mosfet to the in ternal or external clock . this unique controlled on-time architecture is ideal for high step-down ratio applications that demand high switching frequencies and fast transient response. an internal phase lock loop servos the on-time of the internal one-shot timer to match the frequency of the internal clock or an applied external clock. the LTC3626 offers two operational modes: burst mode and forced continuous mode to allow the user to optimize output voltage ripple, noise and light load efficiency for a given application. a pplica t ions n 3.6v to 20v input voltage range n wide output voltage range of 0.6v to 97% v in opti- mized for 0.6v to 6v n low r ds(on) integrated switches provide up to 95% effciency n up to 2.5a of output current n average input and output current monitoring n programmable average input/output current limit n die temperature monitor and programmable limit n adjustable switching frequency: 500khz to 3mhz n external frequency synchronization n current mode operation for excellent line and load transient response n 0.6v reference with 1% accuracy over temperature n user selectable burst mode ? operation or forced continuous operation n short-circuit protected n output voltage tracking capability n power good status output n available in small, thermally enhanced, 20-lead (3mm 4mm) qfn package n distributed power systems n battery-powered instruments n point-of-load power supply l, lt , lt c , lt m , burst mode, linear technology and the linear logo are registered and hot swap is a trademark of linear technology corporation. all other trademarks are the property of their respective owners. protected by u.s. patents, including 5481178, 5847554, 6580258, 6304066, 6476589, 6774611, 5994885. pv in sv in run boost sw v on fb pgood intv cc track/ss ith mode/sync tset imon in tmon imon out sgnd pgnd LTC3626 47f 47f v out 3.3v 2.5a v in 3.6v to 20v 5.1k 1f 2.2f 0.1f 22pf 2.2h 115k 25.5k 3626 ta01 324k rt efficiency vs load current load current (ma) 30 efficiency (%) power loss (w) 90 100 20 10 80 50 70 60 40 1 100 1000 10000 3626 ta01b 0 0.01 10 1 0.1 0.001 10 burst mode operation v in = 12v v in = 5v v out = 3.3v LTC3626 3626fa
2 for more information www.linear.com/LTC3626 a bsolu t e maxi m u m r a t ings pv in ........................................................... C0. 3 v to 22 v sv in ........................................................... C0. 3 v to 22 v boost .................................................... C 0.3 v to 25.6 v boost-sw ................................................ C 0.3 v to 3.6 v intv cc ...................................................... C0. 3 v to 3.6 v ith , rt, fb ................................. C 0.3 v to intv cc + 0.3 v mode / sync .............................. C 0.3 v to intv cc + 0.3 v track / ss , imon in , imon out ... C0.3 v to intv cc + 0.3 v tset , tmon .............................. C 0.3 v to intv cc + 0.3 v sw, run .......................................... C 0.3 v to v in + 0.3 v pgood ....................................................... C 0.3 v to 22 v v on ............................................................ C0. 3 v to 18 v sw source current ( dc , note 2) .............................. 2. 5 a operating junction temperature range ( notes 3, 4) ........................................... C 40 c to 125 c storage temperature range .................. C 65 c to 150 c (note 1) 20 19 18 17 7 8 top view 21 pgnd udc package 20-lead (3mm 4mm) plastic qfn 9 10 6 5 4 3 2 1 11 12 13 14 15 16 boost intv cc v on tset tmon sgnd pv in pv in sv in run rt ith sw sw pgood mode/sync imon in imon out track/ss fb t jmax = 125c, e ja = 47c/w exposed pad (pin 21) is pgnd, must be soldered to pcb p in c on f igura t ion o r d er i n f or m a t ion lead free finish tape and reel part marking* package description temperature range LTC3626eudc#pbf LTC3626eudc#trpbf lgcc 20-lead (3mm = 4mm) plastic qfn C40c to 125c LTC3626iudc#pbf LTC3626iudc#trpbf lgcc 20-lead (3mm = 4mm) plastic qfn C40c to 125c consult ltc marketing for parts specified with wider operating temperature ranges . * the temperature grade is identified by a label on the shipping container . consult ltc marketing for information on non-standard lead based finish parts. for more information on lead free part marking , go to: http://www.linear.com/leadfree/ for more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/ LTC3626 3626fa
3 for more information www.linear.com/LTC3626 e lec t rical c harac t eris t ics the l denotes the specifications which apply over the specified operating junction temperature range, otherwise specifications are at t a = 25c (note 3). pv in = sv in = 12v unless otherwise specified. symbol parameter conditions min typ max units pv in input supply range l 3.0 20 v sv in input supply range l 3.6 20 v v vout output voltage range (note 5) v on = v out 0.6 6 v i q input dc supply current forced continuous operation pv in sv in mode = 0, r rt = 158k, imon in , imon out , tmon, tset = intv cc 30 900 39 1200 a a sleep current pv in sv in v fb > 0.6v, imon in , imon out , tmon, tset, mode = intv cc 30 270 39 350 a a shutdown pv in sv in i load = 0a, v run = 0v 0.01 13 2 17 a a v fb feedback reference voltage l 0.594 0.600 0.606 v ?v line(reg) v fb line regulation pv in = sv vin = 3.6v to 20v 0.01 %/v ?v load(reg) v fb load regulation ith = 0.6v to 1.5v 0.1 % feedback pin input current v fb = 0.6v 30 na error amplifier transconductance ith = 1.2v 1.5 ms t on(min) minimum on-time v von =1v, pv in = sv vin = 3.6v 20 ns t off(min) minimum off-time pv in = sv in = 6v 40 60 ns valley switch current limit 2.4 2.9 3.6 a negative valley switch current limit C1 a f osc oscillator frequency v rt = intv cc r rt = 158k r rt = 105k 1.4 1.7 2.5 2 2 3 2.6 2.3 3.5 mhz mhz mhz r ds(on) top switch on-resistance bottom switch on-resistance 115 70 m m imon out current (note 6) i sw = 2.5a i sw = 1.5a i sw = 0.5a 148.5 89.1 29.7 156.25 93.75 31.25 164.0 98.4 33.5 a a a i out limit regulation voltage l 1.15 1.22 1.28 v imon in current (note 6) i sw = 2.5a, 20% duty cycle i sw = 1.5a, 20% duty cycle i sw = 0.5a, 20% duty cycle 29.7 17.8 5.9 31.25 18.75 6.25 32.8 19.7 6.7 a a a i in limit regulation voltage l 1.15 1.22 1.28 v internal temperature monitor t a = 25c 1.5 v internal temperature monitor slope (note 7) 200 c/v temperature limit hysteresis 50 mv pv in overvoltage lockout threshold pv in rising pv in falling 20 21.5 20.5 v v v intvcc intv cc voltage 3.6v < pv in = sv vin < 20v 3.1 3.3 3.5 v intv cc load regulation (note 8) i intvcc = 0ma to 20ma 0.6 % v run run threshold run rising run falling l l 1.19 0.97 1.23 1.0 1.27 1.03 v v run leakage current pv vin = sv vin = 20v 0 1 a LTC3626 3626fa
4 for more information www.linear.com/LTC3626 e lec t rical c harac t eris t ics the l denotes the specifications which apply over the specified operating junction temperature range, otherwise specifications are at t a = 25c (note 3). pv in = sv in = 12v unless otherwise specified. symbol parameter conditions min typ max units pgood good-to-bad threshold fb rising fb falling 8 C8 10 C10 % % pgood bad-to-good threshold fb rising fb falling C3 3 C5 5 % % power good filter t ime 20 40 s r pgood pgood pull-down resistance 10ma load 20 switch leakage current v run = 0v 0.01 1 a t ss internal soft-start time v fb from 10% to 90% full scale 400 700 s i track/ss track/ss pull-up current 1.4 a mode threshold voltage mode v ih mode v il l l 1.0 0.4 v v sync threshold v oltage sync v ih l 1.4 v mode input current mode = 0v mode = intv cc C1.5 1.5 a a note 1: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. exposure to any absolute maximum rating condition for extended periods may affect device reliability and lifetime. note 2: guaranteed by long term current density limitations. note 3: the LTC3626 is tested under pulsed load conditions such that t j t a . the LTC3626e is guaranteed to meet performance specifications from 0c to 85c. specifications over the C40c to 125c operating junction temperature range are assured by design, characterization, and correlation with statistical process controls. the LTC3626i is guaranteed over the C40c to 125c operating junction temperature range. note that the maximum ambient temperature consistent with these specifications is determined by specific operating conditions in conjunction with board layout, the rated package thermal impedance, and other environmental factors. note 4: this ic includes overtemperature protection that is intended to protect the device during momentary overload conditions. the maximum rated junction temperature will be exceeded when this protection is active. continuous operation above the specified absolute maximum operating junction temperature may impair device reliability or permanently damage the device. note 5: output voltages above 6v are not optimized for controlled on-time operation. refer to the applications information section for further discussions related to the output voltage range. verified at test by comparison of measured on-time to v on voltage. note 6: tested in a proprietary test mode, where i sw flows through the synchronous switch only. note 7: guaranteed by design. note 8: maximum allowed current draw when used as a regulated output is 5ma. this supply is only intended to supply additional dc load currents as needed and not intended to regulate large transient or ac behavior as these waveforms may impact LTC3626 operation. LTC3626 3626fa
5 for more information www.linear.com/LTC3626 typical p er f or m ance c harac t eris t ics efficiency vs input voltage (burst mode operation) efficiency vs frequency (forced continuous mode operation) reference voltage vs temperature internal mosfet r ds(on) vs temperature temperature monitor vs temperature efficiency vs load current (burst mode operation) efficiency vs load current (forced continuous mode operation) efficiency vs load current (burst and forced continuous) load current (ma) 30 efficiency (%) 90 100 20 10 80 50 70 60 40 1 100 1000 10000 3626 g01 0 10 v in = 4v v in = 8v v in = 12v v in = 20v v out = 1.8v load current (ma) 30 efficiency (%) 90 100 20 10 80 50 70 60 40 1 100 1000 10000 3626 g02 0 10 v in = 4v v in = 8v v in = 12v v in = 20v v out = 1.8v load current (ma) 30 efficiency (%) 90 100 20 10 80 50 70 60 40 1 100 1000 10000 3626 g02 0 10 v out = 5v v out = 3.3v burst mode operation forced continuous mode operation input voltage (v) 4 efficiency (%) 80 85 90 20 3626 g04 75 70 60 8 12 16 6 22 10 14 18 65 100 95 i load = 1a i load = 2.5a i load = 100ma i load = 10ma v out = 1.8v load current (ma) 30 efficiency (%) 90 100 20 10 80 50 70 60 40 1 100 1000 10000 3626 g05 0 10 f = 500khz f = 1mhz f = 2mhz f = 3mhz v out = 3.3v temperature (c) ?50 v fb (v) 0.602 0.604 0.606 25 75 3626 g06 0.600 0.598 ?25 0 50 100 125 0.596 0.594 temperature (c) ?50 r ds(on) (m) 140 25 3626 g07 80 40 ?25 0 50 20 0 160 120 100 60 75 100 125 top switch bottom switch temperature (c) ?50 50 75 125 25 75 3626 g08 25 0 ?25 0 50 100 125 ?25 ?50 100 1.6 1.7 2.0 1.5 1.4 1.2 1.1 1.9 measured temperature (c) temperature monitor voltage (v) t a = 25c, pv in = sv in = 12v, f = 1mhz unless otherwise noted. LTC3626 3626fa
6 for more information www.linear.com/LTC3626 typical p er f or m ance c harac t eris t ics quiescent current vs v in (burst mode operation) oscillator frequency vs temperature oscillator internal set frequency vs temperature track/ss pull-up current vs temperature output current monitor error vs output current input current monitor vs input current input current monitor error vs input current output current monitor vs output current output current (a) 0.5 calculated output current, imon out ? 16000 (a) imon out current (a) 1.50 2.00 2.5 3626 g09 1.00 0.50 1.0 1.5 2.0 0.75 1.25 1.75 2.25 2.50 94 125 63 31 156 1.25 1.75 0.75 2.25 t a = 85c t a = 25c t a = C40c output current (a) 1 ?5 measured output current error (%) ?3 ?1 1 1.25 1.5 1.75 2 3626 g10 2.25 3 5 ?4 ?2 0 2 4 2.5 t a = 85c t a = 25c t a = ?40c input current (a) 0.1 calculated input current, imon in ? 16000 (a) imon in current (a) 0.30 0.40 0.5 3626 g11 0.20 0.10 0.2 0.3 0.4 0.15 0.25 0.35 0.45 0.50 19 25 13 6 31 16 22 9 28 0.25 0.35 0.15 0.45 t a = 85c t a = 25c t a = C40c input current (a) 0.16 ?10 measured input current error (%) ?8 ?4 ?2 0 10 4 0.24 0.32 0.36 3626 g12 ?6 6 8 2 0.20 0.28 0.40 0.44 0.48 t a = 85c t a = 25c t a = ?40c input voltage (v) 4 i q (a) 300 400 20 3626 g13 200 100 8 12 16 6 10 14 18 500 250 350 150 450 t a = 85c t a = 25c t a = ?40c temperature (c) ?50 ?10 frequency variation (%) ?8 ?4 ?2 0 10 4 0 50 75 100 3626 g14 ?6 6 8 2 ?25 25 125 r t = 158k temperature (c) ?50 frequency (mhz) 2.2 2.4 2.6 25 75 3626 g15 2.0 1.8 ?25 0 50 100 125 1.6 1.4 r t = intv cc temperature (c) ?50 1.4 1.6 2.0 25 75 3626 g16 1.2 1.0 ?25 0 50 100 125 0.8 0.6 1.8 i track/ss (a) t a = 25c, pv in = sv in = 12v, f = 1mhz unless otherwise noted. LTC3626 3626fa
7 for more information www.linear.com/LTC3626 typical p er f or m ance c harac t eris t ics output tracking start-up from shutdown (burst mode operation) load step (burst mode operation) start-up from shutdown (forced continuous mode operation) load step (forced continuous mode operation) load regulation output voltage vs time (burst mode operation) output voltage vs time (forced continuous mode operation) i load (a) 0 ?v out /v out (%) 0.2 0.6 1.0 2 3626 g17 ?0.2 ?0.6 0 0.4 0.8 ?0.4 ?0.8 ?1.0 0.5 1 1.5 2.5 burst mode operation forced continuous v sw 5v/div v out 20mv/div i l 1a/div 4s/div 3626 g18 v out = 1.8v i load = 100ma v sw 5v/div v out 20mv/div i l 1a/div 2s/div 3626 g19 v out = 1.8v i load = 100ma 2ms/div 3626 g20 v out = 1.8v i load = 200ma v fb v out track/ss 1v/div 500mv/div run 2v/div v out 1v/div i l 1a/div 200s/div 3626 g21 v out = 1.8v i load = 200ma c ss = 2.2nf run 2v/div v out 1v/div i l 1a/div 200s/div 3626 g22 v out = 1.8v i load = 200ma c ss = 2.2nf v out 100mv/div ac-coupled i l 2.5a/div 20s/div 3626 g23 v out = 1.8v c out = 47f i load = 100ma to 2.5a i th = intv cc v out 100mv/div ac-coupled i l 2.5a/div 20s/div 3626 g24 v out = 1.8v c out = 47f i load = 100ma to 2.5a i th = intv cc t a = 25c, pv in = sv in = 12v, f = 1mhz unless otherwise noted. LTC3626 3626fa
8 for more information www.linear.com/LTC3626 p in func t ions boost (pin 1): boosted floating driver supply pin. the (+) terminal of the external bootstrap capacitor connects to this pin while the (C) terminal connects to the sw pin. the normal operation voltage swing of this pin ranges from intv cc to pv in + intv cc . intv cc (pin 2): internal 3.3v regulator output pin. this pin should be decoupled to pgnd with a low esr ceramic capacitor of value 1f or greater. the 3.3v regulator is disabled when the run pin is low. v on (pin 3): on-time voltage input . this pin sets the voltage trip point for the on-time comparator. tying this pin to the output voltage makes the on-time proportional to v out when v out < 6v. when v out > 6v, the switching frequency may become higher than the set frequency . the impedance of this pin is nominally 160k. tset (pin 4): temperature limit set pin . the voltage at this pin determines the threshold for internal temperature shutdown. when the voltage at tmon reaches the volt - age at tset, the LTC3626 will trigger an overtemperature fault. an overtemperature fault will initiate part shutdown , reset soft-start and an attempt to restart once the internal temperature falls 10c ( typical) from the threshold given at tset. the voltage at tset has no impact on a secondary overtemperature shutdown threshold within the LTC3626 as described in note 4 of the electrical characteristics section. tmon (pin 5): temperature monitor output . a voltage proportional to the measured on-die temperature will ap - pear at this pin. the voltage-to-temperature scaling factor is 200 k/v. see the applications information section for detailed information on the tmon function. tie this pin to intv cc to disable the temperature monitor circuit. sgnd (pin 6): signal ground pin. this pin should have a low noise connection to reference ground. the feedback resistor network, external compensation network, current monitor components , and r t resistor should be connected to this ground. imon in (pin 7): average input current monitor. a current proportional to the average input current flows out of this pin. pull this pin to intv cc to defeat the input current moni - tor function . an error amplifier compares the voltage on this pin to 1.2v (typical) and throttles the average current as required based on the external resistor value from this pin to sgnd. selecting the external resistor value allows the user to control the maximum average input current. see the applications information section for more details. imon out (pin 8): average output current monitor pin. a current proportional to the average output current flows out of this pin. pull this pin to intv cc to defeat the output current monitor function. an error amplifier compares the voltage on this pin to 1.2v (typical) and throttles the average current as required based on the external resis - tor value from this pin to sgnd. selecting the external resistor value allows the user to control the maximum average output current . see the applications information section for more details. track/ss (pin 9): output voltage tracking and soft-start input. forcing a voltage below 0.6 v on this pin overrides the internal reference input to the error amplifier. the LTC3626 will servo the fb pin to the track / ss voltage under this condition. above 0.6v, the tracking function stops and the internal reference resumes control of the error amplifier. an internal 1.4a ( typical) pull-up current from intv cc allows a soft-start function to be implemented by connecting an external capacitor between this pin and ground . see the applications information section for more details. fb (pin 10): output voltage feedback . this pin is the input to the error amplifier that compares the feedback voltage to the internal 0.6v reference voltage. connect this pin to the appropriate resistor divider network to program the desired output voltage. LTC3626 3626fa
9 for more information www.linear.com/LTC3626 p in func t ions ith ( pin 11): error amplifier output and switching regula - tor compensation point . connect this pin to appropriate external components to compensate the regulator loop frequency response . connect this pin to intv cc to use the default internal compensation. rt (pin 12): oscillator frequency program pin. connect an external resistor , between 640 k to 105k, from this pin to sgnd to program the LTC3626 switching frequency from 500 khz to 3mhz. when rt is tied to intv cc , the switching frequency will default to 2mhz (typical). run (pin 13): regulator enable pin. enables chip opera - tion by applying a voltage above 1.25v. a voltage below 1.0 v on this pin places the part into shutdown . do not float this pin. sv in (pin 14): signal power supply input. this pin sup- plies current to the internal 3.3v regulator. pv in (pins 15, 16): main power supply input. these pins should be closely decoupled to pgnd with a low esr capacitor of value 10f or more. mode/ sync ( pin 17): mode selection and external synchronization input. this pin places the LTC3626 into forced continuous operation when tied to ground . high efficiency burst mode operation is enabled by either floating this pin or tying this pin to intv cc . when driven with an external clock, an internal phase-locked loop will synchronize the phase and frequency of the internal oscillator to that of incoming clock signal . during external clock synchronization, the LTC3626 will default to forced continuous operation. pgood (pin 18): open-drain power good output pin . pgood is pulled to ground when the voltage at the fb pin is not within 8% (typical) of the internal 0.6 v reference. pgood becomes high impedance once the voltage at the fb pin returns to within 5% (typical) of the internal reference. sw (pins 19, 20): switch node connection to inductor. connect this pin to the sw side of the external inductor. the normal operation voltage swing of this pin ranges from ground to pv in . pgnd ( exposed pad pin 21): power ground pin. the (C) terminal of the input bypass capacitor, c in , and the (C) of the output capacitor, c out , should be tied to this pin with a low impedance connection . this pin must be soldered to the pcb to provide low impedance electrical contact to ground and good thermal contact to the pcb. LTC3626 3626fa
10 for more information www.linear.com/LTC3626 func t ional diagra m rt mode/sync ith imon out imon in pgood r comp c comp r rt osc pv in switch logic and anti- shoot- through i on controller t on = v von i ion r s q on 0.72v 160k 6v run tg m1 l boost m2 bg 0.648v 0.552v track mode/sync 1.25v run intv cc sw pgnd sense ? sense + fb ideal diodes internal soft-start r2 r1 track/ss pv in sv in c in2 r in c bst c intvcc c out c ss 1.4a sgnd c in v on i on ? + ? + ? + run osc pll-sync comp select duty cycle 0.48v at start-up 0.10v after start-up 3.3v reg i cmp i rev a v = 1 ? + ea ? + ? + ? + ov uv ? + ? + 1.2v output current monitor ss 3626 bd 0.6v ref intv cc mode select burst fc ? + ? + temp fault control tset tmon t j 1v/200k LTC3626 3626fa
11 for more information www.linear.com/LTC3626 o pera t ion the LTC3626 is a current mode, monolithic, step-down regulator capable of providing up to 2.5a of output current from an input supply as high as 20v. its unique controlled on-time architecture allows extremely low step-down ratios while maintaining a constant switching frequency. the part is enabled by raising the run pin above 1.25v (typical). main control loop in normal operation the internal top power mosfet is turned on for a fixed interval determined by an internal one-shot timer (on signal in the functional diagram). when the top power mosfet turns off, the bottom power mosfet turns on until the current comparator, i cmp , trips, thus restarting the one-shot timer and initiating the next cycle. the inductor current is monitored by sensing the voltage drop across the bottom power mosfet. the volt - age at the ith node sets the i cmp comparator threshold corresponding to the inductor valley current. the error amplifier, ea, adjusts the ith voltage by comparing an internal 0.6 v reference voltage to the feedback signal, v fb , derived from the output voltage. if, for example, the load current increases, the output voltage will decrease relative to the 0.6v reference. the ith voltage then rises until the average inductor current matches that of the load current . at light load currents the inductor current can drop to zero or become negative. if the LTC3626 is configured for burst mode operation, this inductor current condition is detected by the current reversal comparator, i rev , which in turn shuts off the bottom power mosfet and places the part into a low quiescent current sleep state resulting in discontinuous operation and increased efficiency at low load currents. both power mosfets remain off with the part in sleep and the output capacitor supplying the load current until the ith voltage rises sufficiently to initiate another cycle. discontinuous operation is disabled by tying the mode/sync pin to ground, placing the LTC3626 into for ced continuous mode . in forced continuous mode, continuous synchronous operation occurs regardless of the output load current. the operating frequency is determined by the value of the r t resistor, which programs the current for the internal oscil - lator. an internal phase-locked loop adjusts the switching regulator on-time to track the internal oscillator edge and for ce a constant switching frequency , subject to t on and t off time constraints as shown in the electrical character - istics table. alternatively, the rt pin can be connected to the int v cc pin which causes the internal oscillator to run at the default frequency of 2mhz. finally, a clock signal can be applied to the mode/sync pin to synchronize the switching frequency to an external source . the regulator defaults to forced continuous operation when an external clock signal is applied. output/input current monitor and limit the LTC3626 provides a scaled replica of the average output current and a scaled replica of the average input current at the imon out and imon in pins respectively. the average current at each of these pins will be 1/16,000th of the measured average current. further, the voltage at each pin is continuously fed to independent current limit amplifiers that have a voltage reference at 1.2v. thus, a programmable average current limit for the output current and/or input current may be obtained by placing a resistor of suitable value at the pin of interest so as to produce 1.2v at the desired current limit. when the current limit feature is used, a compensation capacitor (1f typical) should be placed in parallel with the chosen resistor . the output or input current monitor and limit circuits may be individually disabled by pulling imon out or imon in to intv cc as appropriate. LTC3626 3626fa
12 for more information www.linear.com/LTC3626 o pera t ion temperature monitor and limit the LTC3626 produces a voltage at the tmon pin pro - portional to the measured on-die temperature. the on-die temperature-to-voltage scaling factor is 200k/v. thus, to obtain the on-die temperature in degrees kelvin, simply multiply the voltage provided at the tmon pin by the scaling factor . to obtain the on-die temperature in degrees celsius , subtract 273 from the value obtained in degrees kelvin. the voltage produced at tmon is continuously fed to a limit comparator that has the voltage at the tset pin as its reference input. when triggered, this comparator generates an overtemperature fault that will initiate part shutdown and reset of soft-start. thus, a maximum junction temperature limit may be set by providing a voltage at the tset pin that corresponds to the temperature limit of interest. the voltage at the tset pin may be derived from a resistor divider from intv cc , subject to the current constraints listed in the electrical characteristics section, or may be driven externally. the LTC3626 will clear the overtem - perature fault and restart once the internal temperature falls 10c (typical) from the threshold given at tset. the voltage at the tset pin has no impact on the secondary overtemperature shutdown threshold within the LTC3626 as described in note 4 of the electrical characteristics. power good status output the pgood open-drain output will be pulled low if the regulator output exits a 8% window around the regulation point. this condition is released once regulation within a 5% window is achieved. to prevent unwanted pgood glitches during transients or dynamic v out changes, the LTC3626 pgood falling edge includes a filter time of approximately 40s. pv in overvoltage protection to protect the internal power mosfet devices against tran - sient voltage spikes, the LTC3626 continuously monitors the p v in pin for an overvoltage condition . when pv in rises above 21.5v (typical), the regulator suspends operation by shutting off both power mosfets and resets soft-start . once pv in drops below 20.5v (typical), the regulator re- starts normal operation by executing a soft-start. LTC3626 3626fa
13 for more information www.linear.com/LTC3626 a pplica t ions i n f or m a t ion a general LTC3626 application circuit is shown on the first page of this data sheet . external component selection is largely driven by the load requirement and begins with the selection of the inductor l. once the inductor is chosen, the input capacitor, c in , the output capacitor, c out , the internal regulator capacitor, c intvcc , and the boost capaci - tor, c bst , can be selected. next, the feedback resistors are selected to set the desired output voltage. finally, the remaining optional external components can be selected for functions such as external loop compensation, pgood, average output current monitor and limit, average input current monitor and limit, and on-die temperature moni - tor and limit. operating frequency selection of the operating frequency is a trade-off between efficiency and component size. high frequency operation allows the use of smaller inductor and capacitor values. operation at lower frequencies improves efficiency by reducing internal gate charge losses but requires larger inductance values and/or capacitance to maintain low output ripple voltage. the operating frequency, f, of the LTC3626 is determined by an external resistor that is connected between the rt pin and ground. the value of the resistor sets the ramp current that is used to charge and discharge an internal timing capacitor within the oscillator and can be calculated by using the following equation: r rt = 3.2e11 f where r rt is in and f is in hz. connecting the rt pin to intv cc will assert the internal default frequency f = 2mhz; however, this switching fre - quency will be more sensitive to process and temperature variations than using a resistor on r t ( see typical perfor - mance characteristics). the ltc 3626 is not optimized for constant on-time opera - tion when configured to generate output voltages greater than 6v. though output regulation will be maintained under this condition , it is possible the operating frequency may be higher than the programmed value. as a result, for output figure 1. switching frequency vs r t voltages greater than 6v, the value of the r t resistor may need adjustment to obtain the desired operating frequency. inductor selection for a given input and output voltage, the inductor value and operating frequency determine the inductor ripple current. more specifically, the inductor ripple current decreases with higher inductor value or higher operating frequency according to the following equation: ? i l = v out f ? l ? ? ? ? ? ? 1C v out v in ? ? ? ? ? ? where i l = inductor ripple current, v in = pv in , f = operat - ing frequency and l = inductor value . a trade-off between component size, efficiency and operating frequency can be seen from this equation. accepting larger values of i l allows the use of lower value inductors but results in greater core loss in the inductor, greater esr loss in the output capacitor, and larger output ripple. generally, highest efficiency operation is obtained at low operating frequency with small ripple current. a reasonable starting point for setting the ripple current is approximately 1a p-p . note that the largest ripple cur - rent occurs at the highest v in . further, the inductor ripple current must not be so large that the trough or valley reaches the negative valley current limit of C1a (typical) when operating in forced continuous mode . if the inductor current trough reaches the negative current limit while in forced continuous mode operation , v out may exceed the r t (k) 0 2000 2500 3500 300 500 3626 f01 1500 1000 100 200 400 600 700 500 0 3000 frequency (khz) LTC3626 3626fa
14 for more information www.linear.com/LTC3626 a pplica t ions i n f or m a t ion target regulation voltage. to guarantee the ripple current does not exceed a specified maximum the inductance should be chosen according to: l = v out f ? ? i l(max) ? ? ? ? ? ? ? ? 1C v out v in(max) ? ? ? ? ? ? ? ? once the value for l is known, the type of inductor must be selected. actual core loss is independent of core size for a fixed inductor value but is very dependent on the inductance selected . as the inductance increases , core loss decreases. unfortunately, increased inductance requires more turns of wire leading to increased copper loss. ferrite designs exhibit very low core loss and are preferred at high switching frequencies , so design goals can con - centrate on copper loss and preventing saturation. ferrite core materials saturate hard, meaning the inductance collapses abruptly when the peak design current is ex - ceeded. this collapse will result in an abrupt increase in inductor ripple current, so it is important to ensure the core will not saturate. different core materials and shapes will change the size / current and price/current relationship of an inductor. toroidal or shielded pot cores in ferrite or permalloy materials are small and don t radiate much energy but generally cost more than powdered iron core inductors with similar characteristics. the choice of which style inductor to use mainly depends on the price versus size requirements and any radiated field/emi requirements. new designs for surface mount inductors are available from toko , vishay, nec /tokin, cooper, coilcraft, tdk and wrth elektronik. table 1 gives a sampling of available surface mount inductors. c in and c out selection the input capacitance, c in , is needed to filter the trapezoi - dal wave current at the drain of the top power mosfet . t o prevent large voltage transients from occurring , a low esr input capacitor sized for the maximum rms current is recommended. the maximum rms current is given by: i rms = i out(max) v out v in C v out ( ) v in this formula has a maximum at v in = 2v out , where i rms ? i out /2. this simple worst-case condition is com- monly used for design because even significant deviations do not offer much relief . note that ripple current ratings table 1. inductor selection table inductance dcr max current dimensions height vishay ihlp-2525cz-01 series 0.33h 3.5m w 20a 6.5mm 7mm 3mm 0.47h 4.0m w 17.5a 0.68h 5.0m w 15.5a 0.82h 6.7m w 13a 1.0h 9.0m w 11a 1.5h 14m 9a 2.2h 18m 8a 3.3h 28m 6a 4.7h 37m 5.5a 6.8h 54m 4.5a toko fdv0620 series 0.47h 8.3m w 9a 7mm 7.7mm 2.0mm 1h 18.3m w 5.7a nec/tokin mlc0730l series 0.47h 4.5m w 16.6a 6.9mm 7.7mm 3.0mm 0.75h 7.5m w 12.2a 1h 9m w 10.6a cooper hcp0703 series 0.47h 4.2m w 17a 7mm 7.3mm 3.0mm 0.68h 5.5m w 15a 0.82h 8m w 13a 1h 10m w 11a 1.5h 14m w 9a tdk rlf7030 series 1h 8.8m w 6.4a 6.9mm 7.3mm 3.2mm 1.5h 9.6m w 6.1a 2.2h 12m w 5.4a wrth elektronik we-hc 744312 series 0.47h 3.4m w 16a 7mm 7.7mm 3.8mm 0.72h 7.5m w 12a 1h 9.5m w 11a 1.5h 10.5m w 9a LTC3626 3626fa
15 for more information www.linear.com/LTC3626 a pplica t ions i n f or m a t ion from capacitor manufacturers are often based on only 2000 hours of life which makes it advisable to further de- rate the capacitor, or choose a capacitor rated at a higher temperature than required. several capacitors may also be paralleled to meet size or height requirements in the design . for low input voltage applications, sufficient bulk input capacitance is needed to minimize transient effects during output load changes. even though the LTC3626 design includes an overvoltage protection circuit , care must always be taken to ensure input voltage transients do not pose an overvoltage hazard to the part. additional input voltage filtering to the sv in pin (signal v in ) is made possible by adding optional components r in and c in2 as shown in the functional diagram. generally, the inherent supply rejection of the LTC3626 makes the addition of these components unnecessary , however, users with large, asynchronous noise on the input supply may choose to populate these components . typical values for r in and c in2 are 5 and 0.33f respectively. the selection of c out is determined by the effective series resistance ( esr) that is required to minimize voltage ripple and load step transients as well as the amount of bulk capacitance that is necessary to ensure that the control loop is stable. loop stability can be checked by viewing the load transient response. the output ripple, ?v out , is approximated by: ? v out < ? i l esr + 1 8 ? f ? c out ? ? ? ? ? ? when using low esr ceramic capacitors, it is more useful to choose the output capacitor value to fulfill a charge stor - age requirement . during a load step, the output capacitor must instantaneously supply the current to support the load until the feedback loop raises the switch current enough to support the load . the time required for the feedback loop to respond is dependent on the compensation and the output capacitor size. typically , 3 to 4 cycles are required to respond to a load step, but only in the first cycle does the output drop linearly. the output droop, v droop , is usually about 3 times the linear drop of the first cycle. thus, a good place to start is with the output capacitor size of approximately: c out 3 ? ? i out f ? v droop though this equation provides a good approximation, more capacitance may be required depending on the duty cycle and load step requirements. the actual v droop should be verified by applying a load step to the output. using ceramic input and output capacitors higher value, lower cost ceramic capacitors are now available in small case sizes. their high voltage rating and low esr make them ideal for switching regulator ap - plications. however, due to the self-resonant and high-q characteristics of some types of ceramic capacitors, care must be taken when these capacitors are used at the input and output. when a ceramic capacitor is used at the input, and the power is supplied by a wall adapter through long wires, a load step at the output can induce ringing at the v in input. at best, this ringing can couple to the output and be mistaken as loop instability. at worst, a sudden inrush of current through the long wires can potentially cause a voltage spike at v in large enough to damage the part. for a more detailed discussion, refer to application note 88. when choosing the input and output ceramic capacitors choose the x5r or x7r dielectric formulations. these dielectrics provide the best temperature and voltage characteristics for a given value and size. intv cc regulator an internal low dropout ( ldo) regulator produces a 3.3v supply voltage used to power much of the internal LTC3626 circuitry including the power mosfet gate drivers. the intv cc pin connects to the output of this regulator and should have a minimum 1f of decoupling capacitance to ground. the decoupling capacitor should have low impedance electrical connections to the intv cc and pgnd pins to provide the transient currents required by the LTC3626. the user may connect a maximum load current of 5ma to this pin but must take into account the increased power dissipation and die temperature that LTC3626 3626fa
16 for more information www.linear.com/LTC3626 a pplica t ions i n f or m a t ion results. furthermore, this supply is intended only to supply additional dc load currents as desired and not intended to regulate large transient or ac behavior as this may impact LTC3626 operation. boost capacitor the boost capacitor, c bst , on the functional diagram is used to create a voltage rail above the applied input voltage, v in . specifically, the boost capacitor is charged to a voltage equal to approximately intv cc each time the bottom power mosfet is turned on. the charge on this capacitor is then used to supply the required transient current during the remainder of the switching cycle . when the top mosfet is turned on, the boost pin voltage will be equal to approximately v in + 3.3v. for most applica- tions a 0.1f ceramic capacitor will provide adequate per formance. output v oltage programming the LTC3626 will adjust the output voltage such that v fb equals the reference voltage of 0.6v according to: v out = 0.6v 1 + r1 r2 ? ? ? ? ? ? the desired output voltage is set by the appropriate selec - tion of resistors r1 and r2 as shown in figure 2. choosing large values for r 1 and r 2 will result in improved efficiency but may lead to undesired noise coupling or phase margin reduction due to stray capacitance at the fb node. care should be taken to route the fb line away from any noise source, such as the sw or boost lines. to improve the frequency response of the main control loop a feedforward capacitor , c f , may be used as shown in figure 2. minimum off-time/on-time considerations the minimum off-time is the smallest amount of time that the LTC3626 requires to turn on the bottom power mos - fet, trip the current comparator and turn off the power mosfet . this time is typically 40ns. for the controlled on-time current mode control architecture , the minimum off-time limit imposes a maximum duty cycle of: dc max = 1 C (f ? t off(min) ) where f is the switching frequency and t off(min) is the minimum off-time. if the maximum duty cycle is surpassed, due to a dropping input voltage for example, the output will drop out of regulation . the minimum input voltage to avoid this dropout condition is: v in(min) = v out 1C f ? t off(min) ( ) users should consider reducing the LTC3626 operating frequency for applications that may violate the minimum off-time if constant regulation is required. conversely, the minimum on-time is the smallest dura - tion of time in which the top power mosfet can be in its on state. this time is typically 20ns. in continuous mode operation, the minimum on-time limit imposes a minimum duty cycle of: dc min = (f ? t on(min) ) where t on(min) is the minimum on-time. as the equation shows, reducing the operating frequency will alleviate the minimum duty cycle constraint. in rare cases in which the LTC3626s minimum duty cycle is surpassed, the output voltage will still remain in regulation, however the switching frequency will be lower than its programmed value . this is an acceptable result in many applications, so high switching frequencies may be used in the design without fear of severe consequences. as the sections on inductor and capacitor selection show, high switching frequencies allow the use of smaller board components, thus reducing the footprint of the applica - tion circuit. fb r1 r2 c f 3626 f02 v out sgnd LTC3626 figure 2. optional feedforward capacitor LTC3626 3626fa
17 for more information www.linear.com/LTC3626 a pplica t ions i n f or m a t ion internal/external loop compensation the LTC3626 provides the option to use a fixed internal loop compensation network to reduce both the required external component count and design time. the internal loop compensation network can be selected by connect - ing the ith pin to the intv cc pin. to ensure stability, it is recommended that the internal compensation be used at operating frequencies of 1mhz or greater. when using internal compensation, a reasonable starting point for the minimum amount of output capacitance necessary for stability can be found as the greater of either 22f or c out defined by the equation: c out > 70e-6 v out alternatively, the user may choose specific external loop compensation components to optimize the main control loop transient response as desired. external loop com - pensation is chosen by simply connecting the desired network to the ith pin. suggested compensation component values are shown in figure 3. for a 2mhz application, an r-c (r comp and c comp in figure 3) network of 220 pf and 13k provides a good starting point. the bandwidth of the loop increases with decreasing c. if r is increased by the same factor that c is decreased, the zero frequency will be kept the same, thereby keeping the phase the same in the most critical frequency range of the feedback loop. a 10pf bypass capacitor (c byp in figure 3) the ith pin is recom - mended to filter out high frequency coupling from stray board capacitance . in addition, a feedforward capacitor, c f , can be added to improve the high frequency response, as previously shown in figure 2. capacitor c f provides phase lead by creating a high frequency zero with r1 which improves the phase margin. checking transient response the regulator loop response can be checked by observing the response of the system to a load step. when configured for external compensation, the availability of the ith pin not only allows optimization of the control loop behavior but also provides a dc-coupled and ac-filtered closed-loop response test point. the dc step, rise time, and settling behavior at this test point reflect the systems closed- loop response. assuming a predominantly second order system, the phase margin and/ or damping factor can be estimated by observing the percentage of overshoot seen at this pin with a high impedance, low capacitance probe. the ith external components shown in figure 3 will pro - vide an adequate starting point for most applications. the series r-c filter sets the pole-zero loop compensation. the values can be modified slightly, from approximately 0.5 to 2 times their suggested values, to optimize transient response once the final pc layout is done and the particular output capacitor type and value have been determined. the specific output capacitors must be selected because their various types and values determine the loop feedback factor, gain, and phase. an output current pulse of 20% to 100% of full load current , with a rise time of 1 s to 10s, will produce output voltage and ith pin waveforms that will give a sense of the overall loop stability without breaking the feedback loop. when observing the response of v out to a load step, the initial output voltage step may not be within the bandwidth of the feedback loop. as a result, the standard second order overshoot/dc ratio cannot be used to estimate phase margin. the output voltage settling behavior is related to the stability of the closed-loop system and will demonstrate the actual overall supply performance . for a detailed explanation of optimizing the compensation components, including a review of control loop theory, refer to linear technology application note 76. as shown in figure 2 a feed-forward capacitor, c f , may be added across feedback resistor r 1 to improve the high frequency response of the system. capacitor c f provides phase lead by creating a high frequency zero with r1. ith r comp 13k c comp 220pf c byp 3626 f03 sgnd LTC3626 figure 3. compensation components LTC3626 3626fa
18 for more information www.linear.com/LTC3626 a pplica t ions i n f or m a t ion in some applications severe transients can be caused by switching in loads with large (>10f) input capacitors. the discharged input capacitors are effectively put in parallel with c out , causing a rapid drop in v out . no regulator can deliver enough current to prevent this output droop if the switch connecting the load has low resistance and is driven quickly. the solution is to limit the turn-on speed of the load switch driver . a hot swap? controller is designed specifically for this purpose and usually incorporates cur - rent limit, short-circuit protection and soft-start functions. input/output current monitor and limit the LTC3626 senses the average current through the synchronous switch during the on state and outputs a scaled replica of this current (which corresponds to the regulators load current) to the imon out pin. a mirrored version of this signal is modulated with the buck regula - tors duty cycle to provide a scaled replica of the buck regulator s input current to the imon in pin. the average current at each of the monitor pins is 1/16000th the measured average current. the output current at either pin may be measured directly or converted to a voltage with an external resistor. the average input and output current monitor circuits both use a chopping technique to achieve high accuracy. as a result , a small periodic ripple may be seen at either of these outputs, the average of which is the measured value of interest. the ripple frequency will be the operating frequency divided by 256. in addition, the average input current is measured by modulating the duty cycle of the average output current leading to an additional ripple at the operating frequency. if required, a capacitor may be placed on either output pin to reduce the magnitude of the ripple. the voltages at the imon out and imon in pins are con - tinuously fed to independent current limit amplifiers that have a voltage reference of 1.2v ( typical). a programmable average current limit for either average output current or average input current may be obtained by placing a resis - tor, r lim , from the monitor pin to sgnd according to the following equation: r lim = 1.2v ? 16000 i lim where i lim is the programmed current limit. when active, the current limit amplifiers form a feedback loop that controls the maximum average current produced by the LTC3626. thus, when using the current limit fea - ture, a compensation capacitor should be placed between sgnd and the monitor pin of interest . this capacitor, combined with the r lim resistor, is intended to create a dominant pole for compensation purposes. for most ap - plications, a capacitor with a minimum value of 1f will provide adequate loop stability . however, given the wide variation in loop parameters that depend on specific ap - plication requirements, loop stability should be confirmed by stepping the load current to a level that triggers the programmed current limit. the resultant transient response should provide a sense of the overall loop stability with - out breaking the feedback loop. the transient response that results from releasing the current limit should also be checked . if the transient response waveforms exhibit excessive ringing, indicating inadequate loop stability, increase the compensation capacitor value until adequate stability has been achieved. the simple dominant pole compensation scheme dis - cussed previously is intended to provide loop stability by limiting the bandwidth of the current limit feedback loop . as a result , the average current may momentarily exceed the programmed limit until the current limit feedback loop can respond. more advanced compensation networks may be used to potentially reduce the loop response time but generally require more caution and design expertise. for example, one technique is to add a low value resistor in LTC3626 3626fa
19 for more information www.linear.com/LTC3626 a pplica t ions i n f or m a t ion series with the compensation capacitor. the resistor in series with the capacitor creates a zero in the current limit loop transfer function given by: f z = 1 2 ? ? r z ? c while minimally impacting the frequency of the compensa - tion pole. given the current limit loop frequency response contains several moderate frequency poles : one at approxi - mately 10 khz (typical) and two at approximately 100khz (typical), the placement of the zero in frequency can be used to provide additional phase margin, which in turn, may allow a higher loop bandwidth without sacrificing loop stability. for example, choosing c = 0.33f and r z = 50 creates a zero at approximately 10khz thereby reduc - ing the impact of the internal pole located at that same frequency . with this compensation scheme, the LTC3626 current limit loop will have a dominant pole frequency, and overall loop bandwidth, roughly three times higher than that provided with a 1f capacitor, while likely providing adequate loop stability. as previously described, the LTC3626 senses the average output current through the synchronous fet during the off time. as a result, it is recommended the LTC3626 be operated with an off time of greater than 150ns for best current monitor accuracy. for many applications, this is of little concern unless operating at or near regulator dropout conditions (extremely high duty-cycle operation) and high switching frequencies. overall, best current monitor accuracy is achieved with output currents above approximately 200 ma in forced continuous mode with switching frequencies of 1mhz or lower. on-die temperature monitor and limit the LTC3626 produces a voltage at the tmon pin propor - tional to the measured junction temperature. the junction temperature-to-voltage scaling factor is 200k/v. thus, to obtain the junction temperature in degrees kelvin, simply multiply the voltage provided at the tmon pin by the scaling factor. to obtain the junction temperature in degrees celsius, subtract 273 from the value obtained in degrees kelvin. the temperature monitor function uses a chopping tech - nique to achieve high precision. as a result , a small periodic ripple may be seen at the tmon pin , the average of which is the measured value of interest. the ripple frequency will be the operating frequency divided by 32. if required, a 1f or greater capacitor to sgnd may be placed on the output to reduce the magnitude of the ripple. the temperature monitor output is driven from a flexible, internally compensated on-chip buffer capable of sourcing or sinking small amounts of continuous currents (<20a typical). the buffer internal compensation is intended for capacitive loads up to approximately 150pf (typical). this configuration allows direct connection of tmon to convenient test equipment , such as a multimeter, for temperature measurement. the internal compensation may be overridden by connecting a capacitor of value 1f or greater between tmon and sgnd. this configuration allows for a wide range of applications requiring stability with higher load capacitance, such as some adc inputs. the voltage produced at tmon is continuously fed to a limit comparator that has the voltage at the tset pin as its reference input. when triggered, this comparator generates an overtemperature fault that will initiate part shutdown and reset of soft-start. thus, a programmable temperature limit may be obtained by providing a voltage at the tset pin that corresponds to the temperature limit of interest. the voltage at the tset pin may be derived from a resistor divider from intv cc , subject to the current constraints listed in the electrical characteristics section, or may be driven externally. the LTC3626 will clear the overtemperature fault and attempt to restart once the in - ternal temperature falls 10c ( typical) from the threshold given at tset. as an example, to set a temperature limit at approximately 125c, the voltage at tset should be: v tset = 125 c + 273 200 k/v 2v LTC3626 3626fa
20 for more information www.linear.com/LTC3626 a pplica t ions i n f or m a t ion above. during normal operation, if the output drops below 10% of its final value, as it may when tracking down for instance, the regulator will automatically switch to burst mode operation to prevent inductor saturation and improve track/ss pin accuracy. output power good the pgood output of the LTC3626 is driven by a 20 ( typical) open-drain pull-down device. this pin will become high impedance once the output voltage is within 5% (typical) of the target regulation point allowing the volt - age at pgood to rise via an external pull-up resistor. if the output voltage exits a 8% (typical) regulation window around the target regulation point, the open-drain output will pull down to ground , thereby dropping the pgood pin voltage. a filter time of 40s (typical) acts to prevent unwanted pgood output changes during v out transient events. as a result, the output voltage must be within the target regulation window of 5% for 40 s before the pgood pin is pulled high. conversely, the output voltage must exit the 8% regulation window for 40 s before the pgood pin pulls to ground (see figure 4). pgood voltage v out ?8% ?5% 5% 8% 3626 f04 0% nominal output figure 4. pgood pin behavior mode/sync operation the mode/sync pin is a multipurpose pin allowing both mode selection and operating frequency synchronization. connecting this pin to intv cc enables burst mode operation for superior efficiency at low load currents at the expense of slightly higher output voltage ripple . when the mode/ sync pin is pulled to ground, forced continuous mode operation is selected creating the lowest output voltage ripple at the expense of light load efficiency. the LTC3626 will detect the presence of an external clock signal on the mode/ sync pin and synchronize the internal oscillator to the phase and frequency of the incoming clock . the presence of an external clock will place the LTC3626 into forced continuous mode operation. output voltage tracking and soft-start the LTC3626 allows the user to control the output volt - age ramp rate by means of the track/ss pin. from 0v to 0.6 v the track /ss pin will override the internal refer - ence input to the error amplifier forcing regulation of the feedback voltage to that seen at the track / ss pin. when the voltage at the track/ss pin rises above 0.6v, tracking is disabled and the feedback voltage will be regulated to the internal reference voltage. the voltage at the track/ss pin may be driven from an external source , or alternatively, the user may leverage the internal 1.4a (typical) pull-up current on track/ss to implement a soft-start function by connecting a capacitor from the track / ss pin to ground . the relationship between output rise time and track/ss capacitance is given by: t ss = 430,000 ? c track/ss a default internal soft-start timer forces a minimum soft- start time of 400s (typical) by overriding the track/ ss pin input during this time period. hence, capacitance values less than approximately 1000 pf will not significantly affect soft-start behavior. when using the track/ss pin, the regulator defaults to burst mode operation until the output exceeds 80% of its final value (v fb > 0.48v). once the output reaches this voltage, the operating mode of the regulator switches to the mode selected by the mode/sync pin as described efficiency considerations the percent efficiency of a switching regulator is equal to the output power divided by the input power times 100%. it is often useful to analyze individual losses to determine what is limiting the efficiency and which change would produce the most improvement. percent efficiency can be expressed as: % efficiency = 100% C (l1 + l2 + l3 +) where l1, l2, etc. are the individual loss terms as a per - centage of input power. LTC3626 3626fa
21 for more information www.linear.com/LTC3626 a pplica t ions i n f or m a t ion although all dissipative elements in the circuit produce losses, three main sources account for the majority of the losses in the LTC3626: 1) i 2 r loss , 2) switching losses and quiescent current loss , 3) transition losses and other system losses. 1. i 2 r loss is calculated from the dc resistance of the internal switches, r sw , and external inductor, r l . in continuous mode, the average output current will flow through inductor l but is chopped between the internal top and bottom power mosfets . thus, the series resistance looking into the sw pin is a function of both the top and bottom mosfets r ds(on) and the duty cycle (dc) as follows: r sw = (r ds(on)top )(dc) +(r ds(on)bot )(1 C dc) the r ds( on) for both the top and bottom mosfets can be obtained from the typical performance characteristics curves. thus to obtain i 2 r loss: i 2 r loss = i out 2 ? (r sw + r l ) 2. the internal ldo supplies the power to the int v cc rail. the total power loss here is the sum of the switching losses and quiescent current losses from the control circuitry. each time a power mosfet gate is switched from low to high to low again, a packet of charge, dq, moves from sv in to ground . the resulting dq / dt is a current out of intv cc that is typically much larger than the dc control bias current. in continuous mode, i gatechg = f(q t + q b ), where q t and q b are the gate charges of the internal top and bottom power mosfets and f is the switching frequency. for estimation purposes , (q t + q b ) on the LTC3626 is approximately 2.5nc. to calculate the total power loss from the ldo load, simply add the gate charge current and quiescent current and multiply by sv in : p ldo = (i gatechg + i q ) ? v in 3. other hidden losses such as transition loss , cop - per trace resistances, and internal load currents can account for additional efficiency degradations in the overall power system . transition loss arises from the brief amount of time the top power mosfet spends in the saturated region during switch node transitions. other losses, including diode conduction losses during dead time and inductor core losses , generally account for less than 2% total additional loss. thermal considerations the LTC3626 requires the exposed package backplane metal ( pgnd) to be well soldered to the pc board to provide good thermal contact . this gives the qfn package excep - tional thermal properties, compared to other packages of similar size , making it difficult in normal operation to exceed the maximum junction temperature of the part. in many applications, the LTC3626 does not generate much heat due to its high efficiency and low thermal resistance package backplane. however, in applications in which the LTC3626 is running at a high ambient temperature, high input voltage, high switching frequency, and maxi - mum output current , the generated heat may exceed the maximum junction temperature of the part . if the junction temperature reaches approximately 175c, both power switches will be turned off until temperature decreases approximately 10c. thermal analysis should always be performed by the user to ensure the LTC3626 does not exceed the maximum junction temperature. the temperature rise is given by: t rise = p d ? ja where p d is the power dissipated by the regulator and ja is the thermal resistance from the junction of the die to the ambient temperature. consider the example in which an LTC3626eudc is operat - ing with i out = 2.5a, pv in = sv in = 12v, f = 2mhz, v out = 1.8v, and an ambient temperature of 70c. from the t ypical per formance characteristics section the r ds(on) of the top switch is found to be nominally 130m while that of the bottom switch is nominally 85m yielding an equivalent power mosfet resistance r sw of: r ds(on)top ? 1.8 12 + r ds(on)bot ? 10.2 12 = 92m w LTC3626 3626fa
22 for more information www.linear.com/LTC3626 a pplica t ions i n f or m a t ion from the previous section, i gatechg is approximately 5ma when f = 2mhz, and the spec table lists the typical i q to be approximately 1ma. therefore, the total power dissipation due to resistive losses and ldo losses is: p d = i out 2 ? r sw + v in ? (i gatechg + i q ) p d = (2.5a) 2 ? (0.092) + 12v ? 5ma = 635mw the qfn 3 mm 4 mm package junction-to-ambient thermal resistance, ja , is approximately 47c/w. therefore, the junction temperature of the regulator operating in a 70c ambient temperature is approximately: t j = 0.63w ? 47c/w + 70c = 100c which is below the maximum junction temperature of 125c. board layout considerations when laying out the printed circuit board , the following checklist should be used to ensure proper operation of the LTC3626. 1. does the capacitor c in connect to pv in and pgnd as close to the pins as possible? these capacitors provide the ac current to the internal power mosfets . the (C) plate of c in should be closely connected to pgnd and the (C) plate of c out . 2. the output capacitor, c out , and inductor l1 should be closely connected to minimize loss . the (C) plate of c out should be closely connected to pgnd and the (C) plate of c in . 3. the resistive divider, r1 and r2, must be connected between the (+) plate of c out and a ground line termi- nated near sgnd. the feedback signal, v fb , should be routed away from noisy components and traces such as the sw and boost lines, and its trace length should be minimized. in addition, rt , compensation components, and current and temperature monitor/ limit components should be terminated to sgnd. 4. keep sensitive components away from the sw and boost pins. the r rt resistor, the feedback resistors, the compensation components, the current monitor components, and the intv cc bypass capacitor should all be routed away from the sw trace and the inductor. 5. a ground plane is preferred, but if not available the signal and power grounds should be segregated with both connecting to a common, low noise reference point. the point at which the ground terminals of the v in and v out bypass capacitors are connected makes a good, low noise reference point. the connection to the pgnd pin should be made with a minimal resistance trace from the reference point. 6. flood all unused areas on all layers with copper in order to reduce the temperature rise of power components. these copper areas should be connected to the exposed backside connection of the ic. design example as a design example, consider using the LTC3626 in an application with the following specifications: v in = 12v, v out = 1.8v, i out(max) = 2.5a, i out(min) = 50ma further, the ability to continuously monitor the average output current (i out ) and the internal temperature is de- sired. finally, an average i out limit of 2.5 a and an internal temperature limit of approximately 125c are desired. because efficiency is important at both high and low load currents, burst mode operation and 1mhz operation is chosen. first, the correct r rt resistor value for 1mhz switching frequency must be chosen. based on the equation in the applications information section, r rt is calculated to be 320k. a standard 324k resistor is selected for r rt . LTC3626 3626fa
23 for more information www.linear.com/LTC3626 a pplica t ions i n f or m a t ion next, determine the inductor value for approximately 40% ripple current using: l = 1.8v 1mhz ? 1a ? ? ? ? ? ? 1C 1.8v 12v ? ? ? ? ? ? = 1.53h a standard 1.5h inductor will work well for this application. next, c out is selected based on the required output tran - sient performance and the required esr to satisfy the output voltage ripple . for this design, two 22f ceramic capacitors will be used. c in should be sized for a maximum current rating of: i rms = 2.5a ? 1.8v 12v C 1.8v ( ) 12v = 0.89 a decoupling the pv in pin with a 47f ceramic capacitor should be adequate for most applications. an additional 1 f capacitor on the pv in can be used to help reduce ringing as required. a 0.33f capacitor on the sv in pin is optional and will be tied to pv in through a 5 resistor for additional filtering at the sv in pin. finally, a 0.1f boost capacitor should work for most applications. to save board space , the ith pin is connected to intv cc to select the internal compensation network. the pgood pin is connected to v in through a 100 k resis- tor to intv cc . to program the i out limit at 2.5a, a resistor is connected between imon out and sgnd with a desired value equal to: r iout = 16,000 ? 1.2v 2.5a = 7.68k w thus, a standard 7.68k will be selected for r iout . a 1f capacitor placed in parallel with r iout for i out limit loop compensation should be adequate for most applications. the 125 c temperature limit is programmed by setting a voltage at the tset pin equal to: v tset = 125 c + 273 200 k/v 2v in this example, the tset voltage will be derived by divid - ing the available intv cc voltage using r tset1 = 432 k and r tset2 = 665k. pv in sv in run boost sw v on fb rt intv cc track/ss ith mode/sync imon in pgood tmon tset imon out sgnd pgnd LTC3626 c in2 1f c in1 47f r3 5 c3 0.33f v out 1.8v 2.5a v in 12v r iout 7.68k c iout 1f c intvcc 2.2f c bst 0.1f c f 22pf c out 47f l1 1.5h r tset2 665k r tset1 432k r1 40.2k r2 20k r pgd 100k 3626 f07 r t 324k figure 7. 12v input to 1.8v output, 2.5a regulator at 1mhz in burst mode operation with output current monitor and 2.5a limit, on-die temperature monitor and 125c limit LTC3626 3626fa
24 for more information www.linear.com/LTC3626 typical a pplica t ions 12v input to 5v output at 2mhz 5v input to 2.5v output at 1mhz synchronized frequency with input current monitor and 475ma input current limit pv in sv in run boost sw v on fb intv cc rt tset imon out tmon pgood ith imon in sgnd pgnd LTC3626 c1 47f v out 2.5v 2.5a v in 5v c comp 220pf c4 2.2f c iin 1f c bst 0.1f c f 22pf c out 47f l1 2.2h r iin 40.2k r comp 13k r1 127k r2 40.2k external clock r pgd 100k 3626 ta03 track/ss mode/sync pv in sv in run boost sw v on fb mode/sync pgood intv cc rt tset tmon imon in imon out track/ss ith sgnd pgnd LTC3626 c1 47f r3a 5 c3a 0.33f v out 5v 2.5a v in 12v c compa 220pf c4a 2.2f c bsta 0.1f c fa 22pf c outa 47f l1a 1.5h r compa 13k r1a 294k r2a 40.2k pv in sv in run boost sw v on fb mode/sync pgood intv cc rt tset tmon imon in imon out track/ss ith sgnd pgnd LTC3626 r3b 5 c3b 0.33f v out ?5v 1.2a c compb 220pf c4b 2.2f c bstb 0.1f c fb 22pf c outb 47f l1b 1.5h r compb 13k r1b 294k r2b 40.2k c1b 47f LTC3626 3626fa
25 for more information www.linear.com/LTC3626 typical a pplica t ions 12v input to 5v output and 500ma charger for battery backup system pv in sv in run boost sw v on fb intv cc track/ss tmon tset rt ith mode/sync imon in imon out sgnd d5 pgood pgnd LTC3626 c vcc1 2.2f r pg1 100k c in1 47f v in 12v to 20v c bst1 0.1f c f1 22pf c out1 47f l1 1h 5v r fb1 110k r on 0 r fb3 15k pv in sv in boost sw fb imon out v on intvcc track/ss tmon tset rt ith mode/sync imon in sgnd pgood pgnd LTC3626 c vcc2 2.2f r pg2 100k c in2 47f c bst2 0.1f c f2 220pf c out2 47f li-ion battery 4.2v c out3 10f c out4 10f system load 3626 ta05 c iout 1f l2 1h r fb2 1.15m r fb4 191k r d2 1k r1 1k d1 grn r3 1k d3 red r d1 200 r iout 38.3k + in2 clim2 clim1 en1 in1 14 13 12 11 stat2 warn2 warn1 stat1 en2 out2 out1 gnd ltc4415 r2 1k d2 grn r4 1k d4 red 4.2v run charge control LTC3626 3626fa
26 for more information www.linear.com/LTC3626 udc package 20-lead plastic qfn (3mm 4mm) (reference ltc dwg # 05-08-1742 rev ?) 3.00 0.10 1.50 ref 4.00 0.10 note: 1. drawing is not a jedec package outline 2. drawing not to scale 3. all dimensions are in millimeters 4. dimensions of exposed pad on bottom of package do not include mold flash. mold flash, if present, shall not exceed 0.15mm on any side 5. exposed pad shall be solder plated 6. shaded area is only a reference for pin 1 location on the top and bottom of package pin 1 top mark (note 6) 0.40 0.10 19 20 1 2 bottom view?exposed pad 2.50 ref 0.75 0.05 r = 0.115 typ pin 1 notch r = 0.20 or 0.25 45 chamfer 0.25 0.05 0.50 bsc 0.200 ref 0.00 ? 0.05 (udc20) qfn 1106 rev ? recommended solder pad pitch and dimensions apply solder mask to areas that are not soldered 0.70 0.05 0.25 0.05 2.50 ref 3.10 0.05 4.50 0.05 1.50 ref 2.10 0.05 3.50 0.05 package outline r = 0.05 typ 1.65 0.10 2.65 0.10 1.65 0.05 2.65 0.05 0.50 bsc p ackage descrip t ion please refer to http://www .linear.com/designtools/packaging/ for the most recent package drawings. LTC3626 3626fa
27 for more information www.linear.com/LTC3626 information furnished by linear technology corporation is believed to be accurate and reliable . however, no responsibility is assumed for its use. linear technology corporation makes no representa- tion that the interconnection of its circuits as described herein will not infringe on existing patent rights . r evision h is t ory rev date description page number a 05/15 clarified electrical table clarified inductor selection section clarified typical application schematics 3 13 24, 25 LTC3626 3626fa
28 for more information www.linear.com/LTC3626 ? linear technology corporation 2012 lt 0515 rev a ? printed in usa linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 fax : (408) 434-0507 www.linear.com/LTC3626 r ela t e d p ar t s typical a pplica t ion 12v input to 1.8v output, 2.5a regulator with digital output current monitoring pv in sv in run boost sw v on fb mode/sync rt intv cc ith track/ss tset tmon imon in pgood imon out sgnd pgnd LTC3626 c1 47f c2 1f v out 1.8v 2.5a v in 12v c iout 1f c4 2.2f c bst 0.1f c f 22pf c out 47f l1 1.5h r iout 5.1k r1 40.2k r2 20k r pgd 200k 3626 ta04 r t 324k sck sdo cs refout comp ltc2460 gnd ref ? in v cc 0.1f 0.1f 0.1f part number description comments ltc3601 15v, 1.5a (i out ), 4mhz, synchronous step-down dc/dc converter 95% efficiency, v in : 4.5v to 15v, v out(min) = 0.6v, i q = 300a, i sd < 1a, 4mm 4mm qfn-20, msop-16e ltc3603 15v, 2.5a (i out ), 3mhz, synchronous step-down dc/dc converter 95% efficiency, v in : 4.5v to 15v, v out(min) = 0.6v, i q = 75a, i sd < 1a, 4mm 4mm qfn-20, msop-16e ltc3633 15v, dual 3a (i out ), 4mhz, synchronous step-down dc/dc converter 95% efficiency, v in : 3.6v to 15v, v out(min) = 0.6v, i q = 500a, i sd < 15a, 4mm 5mm qfn-28, msop-28e ltc3605a 20v, 5a (i out ), 4mhz, synchronous step-down dc/dc converter 95% efficiency, v in : 4v to 20v, v out(min) = 0.6v, i q = 2ma, i sd < 15a, 4mm 4mm qfn-24 ltc3604 15v, 2.5a (i out ), 4mhz, synchronous step-down dc/dc converter 95% efficiency, v in : 3.6v to 15v, v out(min) = 0.6v, i q = 300a, i sd < 15a, 3mm 3mm qfn-16, msop-16e LTC3626 3626fa

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